The present invention relates to a semiconductor device such as SOI (Silicon on Insulator)--MOSFET and a method of manufacturing the same.
A SOI-MOSFET, which is operable at high speed under a low voltage, exhibits a high driving performance, has a small parasitic capacitance, and is free from soft errors, attracts attentions in this technical field as being highly hopeful in future.
However, the SOI device exhibits a so-called "floating body effect", i.e., the effect produced by the condition that the SOI body is put under an electrically floating state, such as deterioration of the drain breakdown voltage or generation of kink in the static characteristics. In order to put the SOI device into practical use, it is highly important to solve the problem of the floating body effect.
Various measures are being proposed for eliminating the floating body effect. For example, it is proposed to allow the channel region to extend to a region outside the gate region so as to permit the channel region (SOI Body) to be electrically connected to the electrode for body contact. Also proposed is a BTS (Body-Tied-to-Source) structure in which the body is tied to the source. However, the former measure makes the pattern design complex and leads to increases in the element area and gate capacitance. On the other hand, the latter measure causes the source and drain to cease to be interchangeable and brings about reduction in the channel width, leading to a decreased drain current.
Further proposed is an FS (Field Shield) isolation technology, which is said to be capable of solving the above-noted problems and of suppressing the floating body effect.
FIG. 1A is a plan view exemplifying the construction of a conventional device utilizing the FS isolation technology, with FIG. 1B showing a cross section along line 1B--1B shown in FIG. 1A. A reference numeral 51 shown in the drawing denotes a silicon substrate. It is shown that a buried oxide (BOX) layer 52 and a SOI layer 53 are formed on the silicon substrate 51. A SOI substrate consists of these silicon substrate 51, BOX layer 52 and SOI layer 53. Formed on the SOI substrate are a LOCOS isolation layer 54, an FS gate 55 and a transfer gate electrode 56. It should be noted that an electrode 58 for a body contact is connected to the SOI layer 53 through an opening 57a. Also, an electrode (not shown) for contact with the FS gate 55 is connected to the FS gate 55 through an opening 57b. Further, electrodes (not shown) for contact with source and drain regions are connected to the source and drain regions through openings 57c.
The FS isolation technology outlined above makes it possible to achieve a construction which permits the holes accumulated within the channel region, said holes causing the floating gate effect, to flow through a region below the FS gate into the body contact. It is also possible to suppress an increase in the element area, if a well contact region employed in an LSI device having the ordinary bulk silicon substrate is used in the body contact region in the SOI device.
However, the FS isolation technology gives rise to serious problems. First of all, a stepped portion corresponding to the thickness of the FS electrode causes the gate electrode formed on the FS gate to have an irregular surface, making it difficult to process the gate electrode. Also, where the FS gate is present over the entire isolation region and an upper wiring is formed on the isolation region, the capacitive coupling between the upper wiring and the FS gate is increased so as to give a detrimental effect to the operating speed of the device. Further, where a LOCOS isolation or a trench isolation is employed in combination with the FS isolation for decreasing the capacitive coupling, the number of manufacturing steps is markedly increased.